The telecommunications industry continually attempts to improve the transmitter circuitry in wireless communication systems. Power amplifier (PA) circuitry is a major component of a transmitter of a wireless communication device. Power amplifier (PA) circuitry provides the power for transmitting a signal (including data modulated and carried by the signal) so that a base station or a receiver can receive the signal.
Power amplifier (PA) circuitry uses a large amount of power. The power amplifier (PA) module is one of the most power consuming components of a wireless communication device. Therefore it is very desirable to provide power amplifier (PA) circuitry that is power efficient.
A buck/boost switching converter is often used as the VCC power supply for a multiple mode (GSM/EDGE/WCDMA) radio frequency (RF) power amplifier (PA). When a buck/boost switching converter is used, it has to handle different operating modes depending on battery voltage requirements (Vin) and on output voltage (Vout) requirements and one load current (Iload) requirements.
FIG. 1 illustrates a schematic diagram of a simplified prior art buck/boost switching converter circuit 100 (sometimes simply referred to as switcher circuit 100 or as converter 100). The switcher circuit 100 comprises an error amplifier 110 and pulse width modulation (PWM) circuits and driver circuits 120. The inverting input of the error amplifier 110 receives a reference voltage signal VREF and the non-inverting input of the error amplifier 110 receives a feedback voltage signal VFB.
The output of the error amplifier 110 (designated VC) is provided as an input to the PWM and driver circuits 120. A first output line from the PWM and driver circuits 120 controls the operation of a first P-type metal oxide semiconductor (PMOS) transistor M1. A second output line from the PWM and driver circuits 120 controls the operation of a first N-type metal oxide semiconductor (NMOS) transistor M2. A third output line from the PWM and driver circuits 120 controls the operation of a second N-type metal oxide semiconductor (NMOS) transistor M3. A fourth output line from the PWM and driver circuits 120 controls the operation of a second P-type metal oxide semiconductor (PMOS) transistor M4.
The PMOS transistor M1 and the NMOS transistor M2 are connected together as shown in FIG. 1 and are connected to a first end of inductor 130. Power is supplied to the PMOS transistor M1 and to the NMOS transistor M2 by the battery voltage VIN. A typical value of battery voltage VIN is three and six tenths volts (3.6 V). The NMOS transistor M3 and the PMOS transistor M4 are connected together as shown in FIG. 1 and are connected to a second end of inductor 130.
A first end of a first feedback resistor R1 is connected to a node that is located between the PMOS transistor M4 and the output node VOUT of the switcher circuit 100. A first end of an output capacitor C is connected to a node that is located between the first feedback resistor R1 node and the output node VOUT. A second end of output capacitor C is connected to ground.
A second end of the first feedback resistor R1 is connected to a first end of a second feedback resistor that is designated R2. A second end of the second feedback resistor R2 is connected to ground. A feedback line 140 connects the node between the first feedback resistor R1 and the second feedback resistor R2 with the non-inverting input of the error amplifier 110.
It will be assumed that the switcher circuit 100 will be operated in a constant frequency mode (i.e., pulse width modulation (PWM) will be used). Although pulse frequency modulation (PFM) is also often used to provide the power supply in digital microprocessors, pulse frequency modulation (PFM) generates switching noise (or ripple) that is too high for radio frequency (RF) power amplifier (PA) applications. This is particularly so for GSM/EDGE applications.
If the output voltage VOUT is greater than the battery voltage VIN (VOUT>VIN), then the switcher circuit 100 will operate as a boost converter. If the switcher circuit 100 is operated in the boost mode, then the switcher circuit 100 will be in a continuous conduction mode (CCM) as the load current is high.
If the output voltage VOUT is less the battery voltage VIN (VOUT<VIN), then the switcher circuit 100 will operate as a buck converter. One can always run the switcher circuit 100 in a continuous conduction mode (CCM). However, the efficiency of the switcher circuit 100 is lower in the CCM mode than when the switcher circuit 100 is operated in a discontinuous conduction mode (DCM). This is due to additional conduction loss from the buck NMOS transistor M2 when the inductor current is reversed (becomes negative). It is therefore desirable to operate in the discontinuous conduction mode (DCM) to achieve higher efficiency. In the DCM mode the NMOS transistor M2 will stop conducting after the inductor current ramps down to zero.
There are therefore three distinct operating modes for the switcher circuit. The first operating mode is the continuous conduction mode (CCM) boost for high output power (designated CCM boost). The second operating mode is the continuous conduction mode (CCM) buck for medium output power (designated CCM buck). The third operating mode is the discontinuous conduction mode (DCM) for low output power.
It is well known that in radio frequency (RF) power amplifier (PA) applications, higher output power is required to provider higher supply voltages (VCC) to a power amplifier (PA). If the switcher circuit 100 is operated in the boost mode, the switcher circuit 100 is in the continuous conduction mode (CCM) as the load current is high. The feedback loop compensation becomes very difficult to maintain its stability over all of the operating modes and the transition of the modes. This is because the transfer function from the duty cycle control to the output of the switcher circuit 100 is completely different in the three different operating modes.
In the CCM buck mode, the voltage mode converter acts as a double pole from the passive inductor-capacitor (LC) elements. In the CCM boost mode, the voltage mode converter also has a right half plane (RHP) zero in addition to the double pole. The right half plane (RHP) zero makes the feedback loop compensation very difficult. In the DCM buck mode, the voltage mode converter acts as a single low frequency pole.
FIGS. 2A through 2C illustrate typical converter transfer function bode plots (Gvd) from the duty cycle to the output for the three different modes. FIG. 2A shows a typical converter transfer function for the discontinuous conduction mode (DCM) buck mode. FIG. 2B shows a typical converter transfer function for the continuous conduction mode (CCM) buck mode. FIG. 2C shows a typical converter transfer function for the continuous conduction mode (CCM) boost mode.
A simple feedback loop compensation scheme would employ the worst case scenario. A very low frequency dominant pole may be placed uniformly for all of the modes. The loop bandwidth would be low in any condition. This will result in a poor transient performance in all of the conditions.
Therefore, there is a need in the art for a system and method that is capable of providing a remedy for these prior art deficiencies. In particular, there is a need in the art for a system and method that provides an improved architecture for a buck/boost switcher circuit that provides optimized feedback loop compensation.